1. Field of the Invention
The present invention relates generally to a semiconductor memory device having a plurality of memory cells. More particularly, this invention relates to a circuit device for writing data into the memory cells and reading data therefrom.
2. Description of the Related Art
Recent advances in the operational speeds of central processing units have fueled the demand for semiconductor memory devices having faster operational speeds that consume less power than previous semiconductor memory devices. To achieve this, circuits necessary to read and write data to individual memory cells, incorporated in the semiconductor memory device, need to operate at faster speeds while consuming less power than previous read/write circuits.
FIG. 1 illustrates one type of conventional DRAM constructed as a semiconductor memory device. The memory cell array of the DRAM has a plurality of memory cells C (only two shown), and plural pairs of bit lines BL and /BL (only one pair shown) connected to the memory cells C. Word lines WL are connected to the respective memory cells C. When one word line WL is selected by a row decoder (not shown), cell data stored in the associated memory cell C is read onto the associated bit lines BL and /BL.
Sense amplifiers 1 are connected to the associated pairs of bit lines BL and /BL. Each sense amplifier 1 is enabled based on a first and second drive signals .phi.A and .phi.B supplied from a sense amplifier driver 2. The sense amplifier driver 2 outputs the drive signals .phi.A and .phi.B in response to a sense amplifier enable signal .phi.S supplied thereto.
The bit lines BL and /BL are connected via column gates Tr1 and Tr2 to data buses DB and /DB, respectively. A column select signal .phi.Y is input to the column gates Tr1 and Tr2 from a column decoder (not shown). When the column select signal .phi.Y goes high, the column gates Tr1 and Tr2 switch on. In data read mode, cell data amplifier by the sense amplifier 1 is read onto the data buses DB and /DB, and the cell data on the data buses DB and /DB is read out as output data D.sub.out via an output buffer circuit (not shown).
The data buses DB and /DB are connected to a write amplifier 3, which receives write data .phi.DATA and write amplifier enable signals .phi.W. In data write mode, the write amplifier 3 supplies the received write data .phi.DATA onto the data buses DB and /DB in response to the write amplifier enable signal .phi.W. The write data .phi.DATA is written into the selected memory cell C via the data buses DB and /DB, the column gate Tr1 and TR2 and the bit lines BL and /BL.
FIG. 2 shows the sense amplifier 1 and the sense amplifier driver 2. The sense amplifier driver 2 has four inverts 4a to 4d, a P channel MOS transistor Tr3, and N channel MOS transistors Tr4 and Tr5. The inverter 4a receives the sense amplifier enable signal .phi.S. The output terminal of the inverter 4a is connected to the gate of the transistor Tr3 via the two inverts 4c and 4d to the gate of the transistor Tr4, and to the gate of the transistor Tr5 via the inverter 4b. The transistor Tr3 has a source connected to a high potential power supply Vcc and a drain connected to the drain of the transistor Tr4. The transistor Tr5 has a drain connected to the source of the transistor Tr4 and a source connected to a low potential power supply Vss which is grounded. The first drive signal .phi.A is output from the drain of the transistor Tr3, and the second drive signal .phi.B is output from the drain of the transistor Tr5.
When the sense amplifier enable signal .phi.S goes high, the transistors Tr3 and Tr5 switch on and the transistor Tr4 switches off. As a result, the level of the first drive signal .phi.A approximates the potential of the power supply Vcc while the potential of the second drive signal .phi.B nearly reaches that of ground. When the sense amplifier enable signal .phi.S goes low, the transistors Tr3 and Tr5 turn off while the transistor Tr4 turns on. At this time, the potentials of the drive signals .phi.A and .phi.B are both nearly the same.
Since the sense amplifier 1 use a well-known flip-flop circuit construction, its detailed description will be omitted. When the first drive signal .phi.A approaches the potential of the power supply Vcc, and when the second drive signal .phi.B approaches the potential level of the power supply Vss (i.e., around ground level), the sense amplifier 1 is enabled, causing the slight difference in potential existing between the bit lines BL and /BL to increase. When the levels of the drive signals .phi.A and .phi.B become substantially the same, the sense amplifier 1 is disabled and stops functioning.
FIG. 3 shows the structure of the write amplifier 3, which includes three inverters 4e, 4f and 4g and two transfer gates Tr6 and Tr7 each of which are formed using an N channel MOS transistor. The write amplifier enable signal .phi.W is input to the gates of the transfer gates Tr6 and Tr7. When this enable signal .phi.W goes high, the transfer gates Tr6 and Tr7 turn on.
The write data .phi.DATA is supplied to the first transfer gate TR6 via the inverters 4e and 4f and to the second transfer gate Tr7 via the inverter 4g. When both the write amplifier enable signal .phi.W and the write data .phi.DATA are set high, high level data is output on the data bus DB and low level data is output on the data bus /DB. When the write amplifier enable signal .phi.W is high and the write data .phi.DATA is low, low level data is output on the data bus DB and high data is output on the data bus /DB.
The writing operation of the conventional DRAM will now be described with reference to FIG. 4. Normally, in DRAMs, the sense amplifier 1 is enabled even in a mode other than the normal read mode, for the purpose of refreshing cell data. Even in write mode, the sense amplifier 1 may be enabled in response to a high level sense amplifier enable signal .phi.S. With this situation, when the write amplifier enable signal .phi.W goes high, the write data .phi.DATA input to the write amplifier 3 is supplied to the data buses DB and /DB, and is output on the bit lines BL and /BL selected based on the column select signal .phi.Y. The write data on the bit lines BL and /BL is written in the memory cells C selected in accordance with the selection of the word line WL.
According to the conventional DRAM, the sense amplifier 1 is enabled even in a write mode to write data in the memory cells. If the data held in the sense amplifier 1 is complementary to the write data sent to the sense amplifier 1 from the write amplifier 3, the data held in the sense amplifier 1 would be forcibly inverted by the dominant signal from the write amplifier 3. Then, the write data from the write amplifier 3 is written in the selected memory cell via the sense amplifier 1.
With such a construction, a significant amount of time is required for the write amplifier 3 to invert the data held in the sense amplifier 1. Consequently, too much time is needed for the write time t1, including the time needed for its inversion. This leads to lower data writing speeds. In addition, the inversion of the latched data in the enabled sense amplifier 1, produces a flowthrough current in the sense amplifier 1 and increases the output current of the write amplifier 3 to the bit lines BL and /BL, thus increasing the consumed power of the DRAM.